Electronic circuits are typically designed using computer aided design tool. These tools usually are centered around basic building blocks, called “cells”, which represent logic (e.g., a NAND gate), and memory (e.g., a flip-flop). Timing considerations are paramount when designing complex circuits such as very large-scale integrated (“VLSI”) circuits, which can be formed of many millions of cells.
Flip-flops, in particular, require timing considerations related to setup and hold times. The setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data is reliably sampled by the clock. The hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data is reliably sampled. Metastability in flip-flops can be avoided by ensuring that the data and control inputs are in accordance with the setup and hold times. These times are specified in the data sheet for the flip-flop, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices. Computer aided design tools typically include analysis to determine if the setup and hold times are met in all conditions for all flip-flops in a circuit, in order to avoid timing issues.